FIG. 1 is a cross-sectional view of a prior art packaged integrated circuit 10 referred to in the art as leadless plastic chip carrier (LPCC), such as those provided by Amkor of Chandler, Ariz. LPCC 10 includes an exposed die paddle 12 coupled to a copper leadframe 14. Solder plating 16 is formed on the bottom surface of the leadframe 14. Silver plating 18 is formed over the top surface of the leadframe 14. A semiconductor die is attached to the silver plating 18 with a die attach material layer 20. Various gold wire bonds are formed between the top surface of the die and the leadframe 14, such as ground bond 22, down bond 24 and other I/O bonds 26. The structure is overmolded with a mold compound layer 28. The LPCC device is then connected to, for example, a printed circuit board (PCB) (not shown).
The LPCC 10 shown in FIG. 1 tends to suffer from high parasitic inductances, which are induced by the wire bonding, particularly when compared to flip chip bonding techniques described below. These parasitic inductances can impact device performance, particularly with high frequency RF (radio frequency) devices. The LPCC package is also larger than the flip chip package. Of particular concern, the adhesion between the die and the die pad can be poor and the wire bonding pad is easily contaminated by the thin wafer carrier de-bonding/removal process.
There is a continuing effort to increase integrated circuit speed as well as device density. As a result, new packaging schemes have been proposed for packaging complex high speed integrated circuits. One example of such as packaging technique is known as “flip chip” in the art. Various flip chip techniques are described in, for example, U.S. Pat. No. 6,075,712 to McMahon, the entirety of which is hereby incorporated by reference. Flip chip techniques have high package costs and device performance can be improved.
An improved packaging and interconnect scheme are, therefore, desired.